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(1)下载“KX232_PIANO_C5T”文件夹中的sof文件。
(2) 接上串行通信线,与PC机通信。
(3)在“FOR_PC_FILE”文件夹中,双击打开上位机软件“SEND”,按键盘上的“1、2、3.。。”即可弹琴。SEND窗口即显示对应的ASIC码。-(1) Download " KX232_PIANO_C5T" folder in the sof file. (2) connected to the serial communication lines, a
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本文介绍的一种基于多载波扩频通信的Rake接收机工作原理以及设计思想,并用FPGA技术加以实现-This article describes a multi-carrier spread spectrum based communication works as well as Rake receiver design and implementation with FPGA technology to
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it s a document where described rs232 communinication between pc and fpga .
it describe the vhdl structure of uart driver in fpga that allow communication between this devices
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基于VHDL的串行同步通信SPI设计
本设计是用Quartus作为开发环境,以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外,该设计还实现了波特率发生器,数码管显示的功能。用DE2板实现具有电路简洁,开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述,从底层设计,分模块进行,充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous comm
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SPI接口函数,实现双向通讯,速度12Mbps-SPI interface functions, two-way communication, speed of 12Mbps
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基于fpga的串口通信。串行数据收发的同步控制。-Fpga-based serial communication
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rs232通信。vhdl语言编写,能够下载成功-rs232 communication. vhdl language
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用VHDL实现与电脑串口进行通信。已通过开发板验证正确。开发板时钟50M,波特率19200.-VHDL implementation using serial communication with the computer. Has been verified through the development board are correct.
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基于SPARTAN-3E的与计算机的异步串行通信,可根据需要更改波特率等等。-SPARTAN-3E based on the asynchronous serial communication with the computer, according to the need to change the baud rate and so on.
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卷积码是数字通信中很重要的一种差错控制编码 具有很好的性能,用硬件的形式描述具有速度快,便于修改的优点,通过该种方法设,计的编码器经测试运行可靠正确。-Convolutional codes are very important in digital communication error control coding with a good performance, with the descr iption of the hardware in the form of a fast, eas
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基于matlab和vhdl的通信原理gmsk调制算法,主要包括GMSK相位路径的计算,GMSK眼图的仿真以验证相位计算的正确性,正余弦表的量化及bin文件的生成,以及用VHDL硬件语言所描述的基于EPM7128的地址逻辑.-Matlab and vhdl based on the principle gmsk Modulation of communication, including GMSK phase path calculation, GMSK eye diagrams of the s
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VHDL实现RS232串口通信,压缩包内有完整的quartus2工程,由顶层,波特率,发送,接收四个模块构成。外部电路只需要一片MAX232就能与串口助手或单片机通信。-VHDL implementation of RS232 serial communication, compressed within a complete quartus2 project from the top, baud rate, send, receive four modules. External circui
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<基于Verilog HDL的通信系统设计>源码,包含ASK,FSK,PSK,QPSK,PPM等的调制解调-< Verilog HDL-based communication system design> source, including ASK, FSK, PSK, QPSK, PPM and other modem
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基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计,实现其功能,并且能够在FPGA开发平台Quartos上通过仿真验证,证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
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在FPGA实现一个与外围USB FIFO 通信的FIFO控制核-The FPGA to implement a communication with the external USB FIFO FIFO control nuclear
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通用异步通讯UART的工程文档,ISE打开工程,里面有VERILOG的源代码,可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
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FPGA与计算机基于RS232之间的通信-FPGA and RS232-based communication between the computer
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rtl8019以太网通讯,通过FPGA控制-rtl8019 Ethernet communication, and by the control FPGA
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In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this
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学习通信的好资料,串口通信对于收发数据很要!很重要,很重要-Good information to learn communication, serial communication for sending and receiving data is to! Very important, very important
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